Address Translation

Address translation

• PTBR points to the current page table

• n bit virtual address = p bit virtual page offset(VPO) + n-p bit virtual page number(VPN)
• MMU uses the VPN to select the appropriate PTE

• physical and virtual page are both P bytes → physical page offset (PPO) = VPO

page hit & page fault

• page hit(handled entirely by hardware)
1. processor generates a virtual address and sends it to the MMU
2. MMU generates the PTE address and requests it from the cache/main memory
3. The cache/main memory returns the PTE to the MMU
4. The MMU constructs the physical address and sends it to cache/main memory
5. The cache/main memory returns the requested data word to the processor

• page fault(cooperation btw hardware and os kernel)
1. Steps 1 to 3: Same as page hit
2. The valid bit in PTE is zero, so the MMU triggers an exception, which transfers control in the CPU to a page fault exception handler in the os kernel
3. The fault handler identifies a victim page in physical memory, and if the page has been modified, pages it out to disk
4. The fault handler pages in the new page and updates the PTE in memory
5. The fault handler returns to the original process, causing the faulting instruction to be restarted. The CPU resends the offending virtual address to the MMU → Hit!

Speeding up Address Translation with a TLB

• CPU 가 virtual address로 요청할 때 마다, MMU 는 PTE를 참조해야 함. 가장 나쁜 경우에는 memory로부터 추가적인 fetch를 필요로 하게 됨

• L1 cache에 PTE가 있으면 비용이 1, 2사이클 정도로 낮아지겠지만, 많은 시스템은 이러한 비용조차도 제거하기 위해 MMU안에 PTE의 작은 캐쉬를 만듦 (translation lookaside buffer(TLB))

실제 End-to-End translation

1. MMU 가 virtual address로 부터 VPN을 추출하고 TLB가 해당 VPN을 가지고 있는지 확인함
1. TLB에 존재한다면 cache된 PPN(physical page number)을 돌려줌 → PPN과 VPO(from virtual address) 로 부터 physical address를 만들어냄
2. 존재하지 않는다면 메인 메모리로부터 PTE를 가져와야 함

2. 해당 physical address로 부터 메인 메모리에 접근하여 데이터 가져옴