1. Use of the theorems, show that the expression (state the theorems whenever you use them)
(c’+abd+b’d+a’b)(c+ab+cd)
is equal to
(a+c)(a’+c’)+d(b+c).
2. Use the K-map to simplify the following functions as the form in parenthesis.
(a) F(A,B,C) = A(nor)B(nor)C
express in PoS form
(b) F(a,b,c,d) = (pi)M (0, 2 ,6 ,7 ,9 ,12 ,13)*(pi)d (1, 3, 5)
express in SoP form
3. Use a K-map to simplify the function F(x,y,z,w) = (sigma)m (1, 4, 7, 9, 14) with don’t care conditions d(x,y,z,w) = (sigma)d (0, 3 ,5 ,6 ,12).
(a) Find all prime implicants.
(c) Find all essential prime implicants.
(a) What’s the minimal sum of products expression for F?
4. You are given the circuit below. The gate labeled "G" has the minterm expansion given below. Your job is to find the minimum expression for F and draw the optimal two-level circuit. you MUST show the function F in both SoP and PoS forms and address why a certain form leads to more optimal digital logic circuits. You may assume that complementary inputs if needed, are directly available - e.g., both A and NOT A are available
Z(X1, X2, X3) = (sigma)m (0, 1, 4, 5, 6, 7)
5. Suppose that the schematic is restricted to only using NAND gates. Convert the original schematic to a similar one using only NAND gates.
(DON't use NOT gate & complementary inputs)
6. Construct timing charts for the given circuit shown below using the signals given. If a hazard is observed, identify the type of the hazard. Assume the gates have 1 unit of delay.